1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that operates based on the dummy-cell method.
2. Description of the Related Art
In DRAMs (dynamic random access memories), a pair of bit lines are precharged to a middle potential between the power-supply potential and the ground potential, followed by reading data to one of the bit lines, and then amplifying a potential difference between the paired bit lines by use of a sense amplifier so as to sense the data. With the lowering of power-supply potential in recent years, it becomes increasingly difficult to generate a stable middle potential between the power-supply potential and the ground potential. Some technologies have thus been developed to use either a power-supply potential or a ground potential as a precharge potential. A method of reading data in such technologies includes a dummy-cell method.
FIG. 1 is a circuit diagram showing the peripheral circuitry of memory cells operating according to the dummy-cell method.
In the construction of FIG. 1, a pair of bit lines BL and /BL are connected to a sense amplifier 11. The amplification function of the sense amplifier 11 amplifies and holds a differential potential appearing between the bit lines BL and /BL. Each of the bit lines BL and /BL are coupled to memory cells, each of which includes a transistor 12 driven by a word-line potential and a memory cell capacitor 13 for storing data as electric charge. Word lines wl00 through wl(n) correspond to respective word addresses. Each of the bit lines BL and /BL is connected to a single dummy cell. The dummy cell includes a transistor 14 driven by a dummy word line (dwl0C, dwl01), a dummy cell capacitor 15 for storing data as electric charge, and a transistor 16 for precharging the dummy cell capacitor 15. When the transistor 16 becomes conductive by a dummy cell precharging line dcp, a potential vdc is supplied to the dummy cell capacitor 15.
FIG. 2 is a timing chart for explaining a data read operation according to the dummy-cell method.
A bit line bl (collectively representing both of the bit lines BL and /BL) is precharged to a power-supply potential, for example. At timing t1, the dummy cell precharging line dcp is set to HIGH to disconnect the dummy cell capacitor 15 from the potential vdc, thereby finishing precharging of the data-storage node of the dummy cell. At timing t2, the dummy word line dwl is activated (changed to LOW) so as to change the potential of one of the bit lines according to the potential of the dummy cell capacitor 15. At timing t3, the word line wl is activated (changed to LOW) so as to change the potential of the other bit line according to the potential of the memory cell capacitor 13. Timing t2 and timing t3 may be reversed in order, or may be simultaneous. The sense amplifier 11 amplifies a minute potential difference between the bit lines, thereby sending the data.
The bits lines are precharged to the power-supply potential, so that a bit line on which data appears does not exhibit a potential change when HIGH data is being read. In order to achieve proper data reading even in such a case, a potential on the other bit line is dropped by use of a dummy cell, and a resulting differential potential is then amplified to sense the data. The drop of a potential on the bit line caused by the dummy cell needs to be set such that a drop from the power-supply potential is sufficient for sensing of HIGH data, and such that the drop is sufficiently smaller, for sensing of LOW data, than a potential drop on the other bit line that is caused by the LOW data. The dummy cell capacitance is set smaller than the memory cell capacitance. With this provision, a potential difference is generated even when data having the same potential are stored in the dummy cell and the memory cell.
A DRAM suffers gradual loss of data stored in the memory cell capacitor with elapsing of time. Because of this, there is a need to perform constant rewriting operations (refresh operations) for the purpose of retaining the stored data. The dummy cell is disconnected from the bit line at timing t4 by deactivation of the dummy word line dwl. At timing t5, then, the dummy cell precharging line dcp is activated (changed to LOW), thereby writing the set potential vdc. This is referred to as dummy-cell precharge.
Conventionally, the transistor 16 is kept conductive while there is no access to a cell block, thereby constantly writing the set potential to the data storage node of the dummy cell. This is because there was a belief that it is preferable to constantly apply the set potential during the period of no access since the small dummy cell capacitor suffers high-speed loss of stored electric charge.
The shorter the intervals of access to the bit lines, the shorter the precharge time of the dummy cell becomes. This makes it difficult to set a sufficient set potential to the dummy cell. If the access intervals are sufficiently long, on the other hand, a sufficient precharge time ensures that the data storage node of the dummy cell is set to the desired set potential. In this manner, the actual potential of the dummy cell varies, depending on the intervals at which access is made to the bit lines. As a result, the reference potential for data read operation fluctuates, depending on the access intervals, thereby giving rise to a problem in that a data-read margin is reduced.
Accordingly, there is a need for a semiconductor memory device operating based on the dummy-cell method in which a stable read operation is achieved regardless of access intervals.